1. Field of the Invention
This invention relates generally to encoding and decoding digital data and more particularly, to the encoding and decoding of digital data in low power disk drives.
2. Background Information
Digital information stored on a disk drive is typically encoded before the information is written onto the disk. The encoding increases the effective storage density of the disk drive and enables reliable demodulation of the read-back signal. One type of encoding used in storing digital information on a disk drive is called run length limited (RLL) encoding. Typically, RLL codes encode the data so that any two consecutive "ones" in the encoded binary sequence are separated by at least d zeros but no more than k zeroes. The constant d is used to control pulses crowding effects while the constant k is used to provide a self-clocking ability in the read-back of the encoded data. Further, the data is typically blocked into words of length m. Each m bit word is encoded in n bits. The ratio m/n is referred to as the code rate.
In one variation of run length limited encoding, the code rate is 2/3 so that each two consecutive data bits are mapped into three consecutive code bits, which in turn are recorded on the disk. When the data is retrieved from the disk, the serial data stream is converted to three bit code words that are decoded to recreate the original two data bits. Such conventional run length limited ratio 2/3 encoding/decoding systems typically are clocked by a multiplicity of clocks derived from a base clock rate. The base clock rate is the clock frequency used for other components in the disk drive electronics.
Data is clocked from the disk controller to the encoding/decoding system by a data bit clock. The base clock rate is typically divided by three to obtain the data bit clock rate. The encoded data word generated by the encoding/decoding system is clocked by a write clock to the disk. The base clock rate is divided by 2 to obtain the write clock rate.
A prior art example of one data encoding/decoding system is presented in U.S. Pat. No. 4,337,458 entitled "Data Encoding Method and System Employing Two-Thirds Code Rate with Full Word Look-Ahead" issued to Cohn et al. on Jun. 29, 1982. FIG. 1A is a block diagram of encoder 100 of Cohn et al. and FIG. 1B is a block diagram decoder 150 of Cohn et al. Signal CLK (FIGS. 1A and 1B) represents the base clock rate. In encoder 100, base clock rate CLK is divided by 2 to obtain the write clock rate which shifts out the code word from shift register 48. Base clock rate CLK is divided to 3 to obtain the data bit clock rate which shifts data bits into shift register 14. Base clock rate CLK is divided by 6 to obtain the code word clock rate which loads register 22.
Notice that Cohn requires a first shift register 14 to block the serial data into two-bit data words. A second circuit 22 to generate an address that is applied to read-only memory (ROM) 38. ROM 38 based upon the input address encodes the two-bit data word to a three-bit code word and a flag bit F.sub.2. A third shift register 86 is used to serially write the code word to the disk.
Decoder 150 is even more complex. Decoder 150 includes a second ROM and four other circuits 62, 72, 84 and 86. The complexity of this encoding/decoding system and the number of circuits limits its application in miniature low power disk drives because the size of the system requires valuable real estate that cannot be used for other disk drive functions. Further, the complex circuit introduces signal propagation time delays and the related timing jitter.
Electronic circuits in disk drives that utilize encoding/decoding schemes, such as those of Cohn et al. are also disadvantageous because the high base clock rate CLK results in considerable power consumption. Specifically, circuitry which switches more frequently generally consumes more power than does circuitry which switches less frequently. Accordingly, the above described encoding/decoding scheme of the prior art is disadvantageous since it is based on the high frequency of the base clock.
In addition to the power consumption of electronic circuits clocked by a high frequency clock, the frequency of the base clock renders using some data synchronizer and synthesizer chips difficult. Data synchronizer and synthesizers such as the National DP8491, for example, do not have a clock frequency that is three times the data bit clock rate. Rather, the supplied clock clocks at the write clock rate. Accordingly, using the prior art encoding/decoding system requires a dividing the supplied clock rate by 1.5 to generate the required data bit rate clock. Divide by 1.5 circuits typically use both edges of the incoming clock signal. Thus, the supplied clock must have very good clock symmetry. Furthermore, even if the supplied rate clock has a good initial symmetry, this symmetry degrades as the signal passes through a few levels of gating because the high to low and low to high propagation delays through gates and flip-flops differ. Consequently, the prior art encoding/decoding system is effectively limited to systems that have a base clock frequency that is three times the required data bit clock rate.